Passive optical networks (PON) have been developed to provide high bandwidth traffic for subscribers over an optical cable. An exemplary diagram of a typical PON 100 is schematically shown in FIG. 1. The PON 100 includes M optical network units (ONUs) 120-1, 120-2, through 120-M (collectively ONU 120), coupled to an optical line terminal (OLT) 130 via a passive optical splitter 140. Traffic data transmission may be achieved by transmitting data over two optical wavelengths, one for the downstream direction and another for the upstream direction. Downstream transmission from the OLT 130 is broadcasted to all ONUs 120. Each ONU 120 filters its respective data according to, for example, pre-assigned tag values. ONUs 120 transmit respective data to OLT 130 during different time slots allocated by OLT 130 for each ONU 120. Splitter 140 splits a single line into multiple lines, for example, 1 to 32, or, in case of a longer distance from OLT 130 to ONUs 120, 1 to 16.
An ONU includes a PON processor utilized for processing downstream traffic received from the OLT and providing the contents of the downstream traffic to one or more subscriber devices. Similarly, the PON processor of the ONU is designed to receive and transmit upstream data from one or more subscriber devices to the OLT via the passive optical network.
FIG. 2 shows an exemplary diagram of a PON processor 200. The PON processor 200 typically includes a microprocessor 210, a packet processor 220, an Ethernet media access control (MAC) adapter 230, a PON MAC adapter 240, and a memory controller 250 that interacts with an external memory. The various components of the PON processor 200 communicate through an internal bus 260. An example for a PON processor is shown in U.S. Pat. No. 7,643,753 assigned in common to the same assignee as the present application, and is hereby incorporated for all that it contains.
In the architecture of the PON processor 200, there are two logic paths: data and control. In the data path, traffic from/to the PON is processed by the packet processor 220. The processing tasks in the data path include, for exempla, bridge learning, queuing, shaping, and reassembling of packets. Data processed by the packet processor 220 may be either an upstream flow, i.e., data sent from a subscriber device to the OLT or a downstream flow, i.e., data sent from the OLT to a subscriber device. The packet processor 220 is a dedicated piece of hardware designed to accelerate the processing of packets belonging to a certain flow.
In the control path, the microprocessor 210 executes tasks that are typically related to management of connections handled by the PON processor 200. For example, such tasks include, but are not limited to, open/close connections, control the state of a connection, identifying traffic received on a new connection, and so on. Such operations generally do not require processing of individual packets belonging to a certain flow. For example, if the microprocessor 210 indentifies a packet received on a new connection, then the processing of the first packet will be performed by the microprocessor 210 and subsequence packets are handled only by the packet processor 220.
In addition to different processing tasks performed by the packet processor 220 and microprocessor 210, each processor is programmable differently. Specifically, in order to allow fast processing of traffic, the packet processor 220 is programmable using firmware, which comprises low-level execution code (e.g., assembly or any proprietary programming language). The firmware includes instructions purposely designed to accelerate the processing tasks of the packet processor 220. The firmware is developed by the vendor of the PON processor 200 and is integrated therein prior to the installation of the PON processor 200 in an ONU. Thus, any modifications in the firmware can be made by the vendor of the PON processor 200.
The microprocessor 210 is typically a general-purpose central processing unit (CPU) that is programmable to execute software that includes high-level programming language (e.g., C) over an operation system. Any modifications to the software of the microprocessor 210 can be performed on-site, for example, by a novice technician of the ONU, by re-programming the software of the microprocessor 210.
On one hand, even a high-performance microprocessor cannot execute processing tasks as fast as dedicated processors, i.e., the packet processor 220. On the other hand, dedicated processors are not as flexible as general-purpose CPUs. For example, if a new processing task should be performed in the data path, the firmware should be re-programmed and re-installed on the PON processor 200. The lack of flexibility in such architectures is a major drawback for the network providers, as once the PON processors 200 are installed in the ONUs 120, modifications to the processing tasks cannot easily be performed on-site.
Thus, it would be highly advantageous to provide programmable network processors that can easily be modified and on-site.